|Spartan-7 FPGA Board DS#T0006 REV 2021/07/09 PDF version (coming soon), HTML version|
|Small form factor FPGA module
with Xilinx Spartan-7
The photos below show both sides of the small form factor Spartan-7 FPGA Module (equipped with Xilinx XC7S25-1FTGB196). By default, the board is not populated with pin headers on the 2.54 mm grid.
The small form factor Spartan-7 FPGA Module is an out-of-the-box feature FPGA board with only 2″ x 2″ (50.8 mm x 50.8 mm) dimensions. It is ready for use by simply connecting a power supply and programming the FPGA or the 64 Mbit SPI flash via the standard Xilinx JTAG connector. The board operates with a USB power supply or an external power supply sourced either by the screw terminal P1 or the pin grid. The module supports a wide input voltage range from 5 V up to 17 VDC and provides 83 general purpose IOs (GPIOs) through easily accessible pin grids at the edges of the board. Additionally there is a dedicated input for analog-to-digital conversion with a sample rate of up to 1 MSPS and a resolution of 12 bit (built-in Xilinx XADC module). The onboard USB-UART bridge allows communication to a host with datarates up to 3 MBaud. Further, the Spartan-7 FPGA Module has four programmable blue LEDs and four micro switches for user interactions. The board includes a stable 100 MHz system clock source for the FPGA, but which also can be clocked from external sources via pin connectors. Finally, the board offers all basic functions for many FPGA applications on a tiny footprint without the need for an additional carrier board.
|2. Application information
2.1. Powering the board
The board can be powered via the USB connector J1 or via an appropriate voltage (5 V to 17 V) at the screw terminal P1. It is not recommended to use both power supply inputs simultaneously! If possible, the USB power supply by a host should be deactivated when using the screw terminals for powering the board. With sufficient caution, however, both voltage inputs can also be used in parallel. A test with 17 V input voltage and additional USB power supply showed no damage or impairments. Be careful and make sure that the power supply is connected with the correct polarity! The board has no further input protection circuit for an incorrect connection. The ports of the screw terminal P1 are marked with + and - signs on silkscreen layer (in future version, not yet in rev. A). Fig. 1 shows the right polarity. Fig. 1: Take care of the right polarity of the screw terminal power input P1. The positive terminal is located left.
Another way to power the Spartan-7 board is to use the dedicated pins of the pin grid (see Fig. 2). Pin 1 of each grid (square shape) can be used as main voltage input or output. The corresponding Ground (GND) is pin 2. Supply via these pins corresponds functionally to supply via the screw terminal P1. The valid input voltage range is 5 V to 17 V! The main purpose of these pins is to supply further slave modules or other devices. That means, these pins are intended as voltage output! It is possible to supply the FPGA module itself via these pins, but this should not be the preferred usage. With a power supply via the USB connector, the output voltage at pin 1 of the pin grid is approx. 5 V. When external voltage is applied to the screw terminal P1, this voltage will appear on the pins. Fig. 2: Pin number markings on the connector grid. Pin 1 of each grid can be used as a power supply output or input. Pin 2 is the corresponding ground (GND). 2.1. Programming the board
Our Spartan-7 FPGA Module is supported by the free Xilinx Vivado HL WebPack Edition since Version 2018.1. Code can be synthesized and finally downloaded to the FPGA with the Xilinx toolchain. For this purpose, we recommend a supported programming cable like Xilinx Platform Cable USB or JTAG-HS3 Programming Cable from Digilent. Your cable must fit into the standard Xilinx JTAG header with 14 pins. Some examples are shown in Fig. 3 below. Fig. 3: Onboard standard Xilinx JTAG header (left) with plugged Digilent JTAG-HS3 Programming Cable (middle) or Xilinx Platform Cable USB (right) The possibilities to program the FPGA are numerous and depend on the preferences of the user. In the simplest case you use the Hardware Manager from Xilinx Vivado and program the FPGA directly with a bit-file. For a non-volatile configuration of the FPGA you have to program a valid configuration file to the onboard SPI flash. The configuration memory is an IC of S25FL064L series from Cypress Semiconductor. In the Hardware Manager from Xilinx Vivado you have to choose the type s25fl064l-spi-x1_x2_x4 (see Fig. 4.). Please note that the Flash memory is only supported since Vivado version 2017.3. Fig. 4: Choose the right configuration memory part in Xilinx Vivado. The S25FL064L series is supported since Vivado version 2017.3. You can check proper device functionality by reading XADC values like internal voltage levels or device temperature (see Fig. 5) Fig. 5: Xilinx Vivado Hardware Manager can be used to read internal XADC values from the FPGA module. After you have powered up the board and downloaded the reference design from GitHub (coming soon) to the board, the four user LEDS starts to blink. Fig. 6: A "hello world" reference design with blinking LEDs is available at GitHub (coming soon).
|3. Electrical data (pin description)
Fig. 7: An overview of all building blocks of Spartan-7 FPGA board.
0. FPGA The board is assembled with a Xilinx Spartan-7 FPGA XC7S25-1FTGB196C. The speed grade of this device is -1 and operating temperture range is 0°C .. 85°C (commercial grade). Other assemblies are available on request (see Ordering information). A master XDC constraint file is available at GitHub (https://github.com/iamelectronic/T0006_Spartan_7_Hello_World) as well as a reference sample project for Xilinx Vivado.
1. P1 screw terminal The screw terminal P1 is for direct power supply with loose cables. Recommended wire range (AWG) is 16 - 28. The wire strip length should be 3-4mm. The circuitry is designed for an input voltage of 5 V to 17 V. Make sure the polarity is correct when connecting the cables! Fig. 8: Screw terminal P1 for power input (front view). Left port is positive terminal, right is negative (GND).
2. JTAG header The pin assignment of the JTAG header matches the 14 pin pos. connectors of common programming cables. Some examples have been shown in section 2.1. Programming the board. Fig. 9: Standard Xilinx JTAG Header, dual row with 14 pins (2.00 mm pitch).
3. User LEDs (blue) Besides the FPGA there is a row of four blue LEDS. They are marked with designators LD1, LD2, LD3, and LD4. The output drivers of the FPGA pins are used to power the LEDs directly through a 100 Ω series resistor. Tab. 3 shows the output pins from the FPGA connected to the LEDs. Fig. 10: User LEDs (blue) LD1, LD2, LD3, and LD4.
4. Configuration LED LD0 indicates completion of the configuration sequence. After programming has finished, the LED will be on (until the FPGA is configured, the LED will be off). In normal operation the LED LD0 is permanently switch on. Fig. 11: User LEDs (blue) LD1, LD2, LD3, and LD4.
5. Reset button The button SW1 next to the JTAG connector triggers a manual reset of the FPGA. Fig. 12: Reset button SW1. In the unpressed state the PROGRAM_B pin of the FPGA is pulled high, and while pushing the button this pin is tied to GND. On falling edge, the FPGA configuration is cleared and configuration sequence is initiated upon the following rising edge. Because the FPGA is permanently configured to Master SPI mode, a new sequence will load configuration data from SPI flash.
6. Micro switches The four micro DIP switches SW2 can be used for user inputs. Fig. 13: Micro DIP switches SW2. Due to the small dimensions of the switches, these can probably be used for coding fixed values or states rather than for user inputs. During OFF-state of the switches, the associated pins of the FPGA are pulled high. In ON-state, they are tied to GND. The ON position of the switches is marked on the case, and the assigned pins are shown in Tab. 6.
7. Configuration memory (SPI flash) The non-volatile configuration for the FPGA can only be loaded in Master SPI mode (FPGA pins M[2:0]=001) from the attached memory device U2 (SPI flash). Fig. 14: 64 Mbit SPI configuration flash. During configuration, internal pull-up resistors are disabled on each SelectIO pin, because pin B10 IO_L3P_T0_DQS_PUDC_B is permanently pulled high. The flash is from S25FL064L series from Cypress Semiconductor. Since Xilinx Vivado version 2017.3 these series is supported (see Xilinx UG908, Table C-3: Supported Flash Memory Devices for Spartan-7 Device Configuration). The flash memory has a density of 64 Mbit. The entire configuration bitstream length for the Xilinx XC7A35T is 17,536,096 bit (see Xilinx UG470, Table 1-1: Bitstream Length). In Xilinx Vivado, you have to choose s25fl064l-spi-x1_x2_x4 device for configuration memory (see section 2.1. Programming the board for details). The FPGA pins used to control the SPI flash are listed in Tab. 7
8. Clock source 100 MHz A Low-Jitter precision oscillator generates a stable system clock for the FPGA. The board has a DSC1101CI5-100.0000 MEMS oscillator (U3) from Mirochip with 100 MHz output clock frequency. Fig. 15: 100 MHz clock source. The operating temperature is from -40°C to 85°C with a frequency stability of ±10 ppm. The clock soure has a signle ended CMOS Output (High = min. 2.97 V, Low = max. 0.33 V). The output is directly routed to a Multi-region Clock Capable (MRCC) clock input on bank 14 (see Tab. 8).
9. USB-UART Bridge The board includes a CP2102 Single-Chip USB to UART bridge from Silicon Labs. The devices has designator U7 and is located on bottom side of the board. The utilized CP2102N-A01-GQFN20 chip can transmit data with a maximum baud rate of 3 Mbaud. Please download the CP210x Virtual Com Port (VCP) drivers from silabs.com. After installing the drivers, you can communicate with your FPGA via a virtual COM port of the operating system. Fig. 16: USB-UART bridge CP2102N-A01-GQFN20 (U7) Fig. 17: USB-UART bridge connector J1
A. IO grid PN (NORTH, 32 pins) The pin grid on the upper side of the board (NORTH) has 32 pins with 2.54 mm pitch. There are 24 General Purpose IOs (GPIOs), three Vout pins with 3.3V, one VIN/VOUT pin (described in 2.1. Powering the board) and four Ground (GND) pins in total. All IOs are connected to a bank powered at 3.3 V. Fig. 16: PN pin grid with 32 positions.
B. IO grid PE (EAST, 32 pins) The pin grid on the right side of the board (EAST) has 32 pins with 2.54 mm pitch. There are 24 General Purpose IOs (GPIOs), three Vout pins with 3.3V, one VIN/VOUT pin (described in 2.1. Powering the board) and four Ground (GND) pins in total. All IOs are connected to a bank powered at 3.3 V. Fig. 16: PE pin grid with 32 positions.
C. IO grid PS (SOUTH, 16 pins) The pin grid on the lower side of the board (SOUTH) has 16 pins with 2.54 mm pitch. There are 14 General Purpose IOs (GPIOs), one VIN/VOUT pin (described in 2.1. Powering the board) and one Ground (GND) pins in total. All IOs are connected to a bank powered at 3.3 V. Fig. 16: PS pin grid with 16 positions.
A. IO grid PW (WEST, 32 pins) The pin grid on the left side of the board (WEST) has 32 pins with 2.54 mm pitch. There are 21 General Purpose IOs (GPIOs), one analog input (differential), three Vout pins with 3.3V, one VIN/VOUT pin (described in 2.1. Powering the board), one state pin, and four Ground (GND) pins in total. All IOs are connected to a bank powered at 3.3 V. Fig. 16: PW pin grid with 32 positions.
E. DC/DC converter for I/O voltage All I/O banks (bank 0, 14, and 34) of the FPGA are powered by 3.3 V. The voltage is provided by an onboard DC/DC converter which is capable of driving an output current of 2 A. All current sinks connected to the board and the FPGA itself must be considered to not exceed the current limit of 2 A! Further, we recommend the following constraints regarding the configuration of the FPGA: set_property CFGBVS VCCO [current_design]; set_property CONFIG_VOLTAGE 3.3 [current_design]; For single ended IO we recommend following constraint template for IOSTANDARD of a pin: set_property IOSTANDARD LVCMOS33 [get_ports *]; and for differential IO use Transition Minimized Differential Signaling (TMDS) standard: set_property IOSTANDARD TMDS_33 [get_ports *];
|4. Typical characteristics
to be done after first mass production run!
|5. Mechanical data
Following drawings show relevant mechanical dimensions of the board. All dimensions are in millimeters (mm). Fig. 18: Mechanical dimension of the FPGA module (board outline and mounting holes).
|6. Ordering information
The T0006 Spartan-7 FPGA Module can be ordered at various online market places, or you can request a quotation by sending an e-mail to email@example.com.
Tab. 12: Assembly variants of Spartan-7 FPGA Module with product numbers and market places.
|7. Document history Document number: DS#T0006 Version history: 2021/09/17: Added link to schematics pdf file in section 3. 2021/07/09: Fixed pin locations of 100MHz clock input. 2019/12/18: Changed 100MHz clock input pin in Tab. 8 for Board REV. B 2019, changed Pinout for PE Pin 18 in Tab. 9, all changes apply to Board REV. B 2019, added link to master XDC file at Github in Sec. 3.0 FPGA 2019/12/11: Fixed board pin names in tab. 9 (changed from PN pin xyz to PW pin xyz), and updated ordering information 2018/08/23: Added online market places in section 6. Ordering information 2018/08/7: Initial release|
|8. Imprint Name and registered office of the company: IAM Electronic GmbH Bucksdorffstr. 43 04159 Leipzig Germany Contact: Phone: +49 341 26496031 E-Mail: firstname.lastname@example.org Chief Executive Officer: Dr. Philipp Födisch Commercial register: Register court: Amtsgericht Leipzig Register number: HRB 34071 Value Added Tax Identification Number: DE313797981|