FPGA Mezzanine Card (FMC) Clock Generator

314.00 

Features

  • Skyworks Solutions (Si Labs) Si5394, Any-Frequency, Any-Output Jitter Attenuator / Clock Multiplier
  • Low-pin count (LPC) connector
  • 4 SMA connectors for clock outputs:
    • 2 independent differential clocks or
      • Output frequency range (differential): 100 Hz to 1028 MHz
    • 2 independent complementary / in-phase LVCMOS clocks (4 outputs):
      • Output frequency range (LVCMOS): 100 Hz to 250 MHz
  • 1 SMA connector for external clock reference:
    • External reference frequency input: 8 kHz to 250 MHz
  • 1 differential clock from FPGA Mezannine Card to FPGA carrier’s GPIO
  • 1 differential clock from FPGA Mezannine Card to FPGA carrier’s Gigabit-Transceiver
  • 5 LEDs for status outputs
  • EEPROM for FRU information storage
  • ANSI/VITA 57.1 compliant
  • Open-source hardware
SKU: T0013 Category:

Description

The FMC clock generator is a four-channel, any frequency, any output clock synthesizer. It is based on the Si5394A from Skyworks Solutions (formerly: Si, Silicon Labs). The Si5394A delivers ultra-low jitter (down to 69 fs). It is used in applications that require the highest level of jitter performance. All clock generation components are located on a single-width FPGA mezzanine card (FMC). The FMC module generates a total of 4 independent clock frequencies. Two clock frequencies are accessible via the SMA connectors on the front panel. There you can use either differential signals or LVCMOS compatible voltage levels. The remaining two clock outputs of the Si5394A are routed to the FMC connector. The FPGA uses these clocks to clock general purpose logic and multigigabit transceivers. All generated clocks can be synchronized to an external clock reference. The board is ANSI/VITA 57.1 compliant.

Applications

  • Ultra-low jitter clocking
  • Frequency synthesis
  • Jitter cleaning
  • Device synchronization
  • High-speed data acquisition systems
  • Test and measurement

Features

  • Skyworks Solutions (Si Labs) Si5394, Any-Frequency, Any-Output Jitter Attenuator / Clock Multiplier
  • Low-pin count (LPC) connector
  • 4 SMA connectors for clock outputs:
    • 2 independent differential clocks or
      • Output frequency range (differential): 100 Hz to 1028 MHz
    • 2 independent complementary / in-phase LVCMOS clocks (4 outputs):
      • Output frequency range (LVCMOS): 100 Hz to 250 MHz
  • 1 SMA connector for external clock reference:
    • External reference frequency input: 8 kHz to 250 MHz
  • 1 differential clock from FPGA Mezannine Card to FPGA carrier’s GPIO
  • 1 differential clock from FPGA Mezannine Card to FPGA carrier’s Gigabit-Transceiver
  • 5 LEDs for status outputs
  • EEPROM for FRU information storage
  • ANSI/VITA 57.1 compliant
  • Open-source hardware

Additional information

Weight 71 g
Dimensions 84.0 × 69.0 × 14.5 mm
Repository

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Wiki

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Country of Origin

Germany

Harmonised Code

8542 3119

ECCN

NOCLASS