|Artix-7 FPGA Module DS#T0005 REV 2018/04/17 PDF version (coming soon), HTML version|
|Tiny 5 x 5 cm² FPGA module
with Xilinx Artix-7
The photos below show both sides of the Artix-7 FPGA Module (equipped with Xilinx XC7A35T-1FTG256C). By default, the board is not populated with the two optional MMCX jacks for differential clocking (Input or Output).
The tiny Artix-7 FPGA Module is an out-of-the-box feature FPGA board with only 5 cm x 5 cm dimensions. It is ready for use by simply connecting a power supply and programming the FPGA or the 64 Mbit SPI flash via the standard Xilinx JTAG connector. The board operates with a wide input voltage range from 5 V up to 17 VDC sourced either by the screw terminal or pin 1 from the PT header (26 pos. male header). The module provides 36 general purpose IOs (GPIOs) through two easily accessible pin headers. Some of the inputs can be used for analog-to-digital conversion with a sample rate of up to 1 MSPS and a resolution of 12 bit (built-in Xilinx XADC module). For connecting auxiliary modules to the connectors, the board includes hardware-selectable power pins. Further, the tiny FPGA module has four programmable LEDs (one green and one red LED, two blue LEDs) and four micro switches for user interactions. On the board is a stable 100 MHz system clock source for the FPGA, but which also can be clocked from external sources via the connectors. Finally, the board offers all basic functions for many FPGA applications on a tiny footprint without the need for an additional carrier board.
|2. Application information
2.1. Powering the board
Be careful and make sure that the power supply is connected with the correct polarity! The ports of the screw terminal P1 are marked with + and - signs on silkscreen layer. Fig. 1 shows the right polarity. Fig. 1: Take care of the right polarity of the screw terminal power input P1. The positive terminal is located left.
Another way to power the Artix-7 FPGA Module is to use pin 1 and pin 2 of the PT header. By default, pin 1 is shorted with the positive input port (VIN) of the screw terminal, and pin 2 is shorted with GND. This configuration can be used to power the board either by the pins of the PT header or the screw terminal P1. Do not connect a voltage source to both power inputs P1 and PT header pins 1 and 2 at same time! But you can power the FPGA module via P1 (VIN and GND) and a slave module connected to the PT header pin 1 and 2(VIN and GND). Fig. 2 shows the resistors used for hardware-selectable configuration of PT and PR header. All suitable configurations are summarized in Tab. 1. Fig. 2. Default configuration for PT header (left image): RS1 shorts VIN to pin 1. Default configuration for PR header (right image): RS3 shorts 3.3V from DC/DC switch to pin 1. Tab. 1: Hardware-selectable voltage configuration. Pin 1 of headers PT and PR is set by resistor jumpers RS_.
Our Artix-7 FPGA Module is supported by the free Xilinx Vivado HL WebPack Edition. Code can be synthesized and finally downloaded to the FPGA with the Xilinx toolchain. For this purpose, we recommend a supported programming cable like Xilinx Platform Cable USB or JTAG-HS3 Programming Cable from Digilent. Your cable must fit into the standard Xilinx JTAG header with 14 pins. Some examples are shown in Fig. 3 below. Fig. 3: Onboard standard Xilinx JTAG header (left) with plugged Digilent JTAG-HS3 Programming Cable (middle) or Xilinx Platform Cable USB (right) The possibilities to program the FPGA are numerous and depend on the preferences of the user. In the simplest case you use the Hardware Manager from Xilinx Vivado and program the FPGA directly with a bit-file. For a non-volatile configuration of the FPGA you have to program a valid configuration file to the onboard SPI flash. The configuration memory is an IC of S25FL064L series from Cypress Semiconductor. In the Hardware Manager from Xilinx Vivado you have to choose the type s25fl064l-spi-x1_x2_x4 (see Fig. 4.). Please note that this device is only supported since Vivado version 2017.3. Fig. 4: Choose the right configuration memory part in Xilinx Vivado. The S25FL064L series is supported since Vivado version 2017.3. You can check proper device functionality by reading XADC values like internal voltage levels (see Fig. 5) Fig. 5: Xilinx Vivado Hardware Manager can be used to read internal XADC values from the FPGA module. After you have powered up the board and downloaded the reference design from GitHub (coming soon) to the board, the four user LEDS starts to blink. Fig. 6: A "hello world" reference design with blinking LEDs is available at GitHub (coming soon).
|3. Electrical data (pin description)
Fig. 7: An overview of all building blocks of the tiny FPGA board.
0. FPGA The board is assembled with a Xilinx Artix-7 FPGA XC7A35T-1FTG256C. The speed grade of this device is -1 and operating temperture range is 0°C .. 85°C (commercial grade). Other assemblies are available on request (see Ordering information). A master XDC constraint file is available at GitHub (coming soon) as well as a reference sample project for Xilinx Vivado.
1. P1 screw terminal The screw terminal P1 is for direct power supply with loose cables. Recommended wire range (AWG) is 14 - 22. The wire strip length should be 5-6mm. The circuitry is designed for an input voltage of 5 V to 17 V. Make sure the polarity is correct when connecting the cables! Fig. 8: Screw terminal P1 for power input (front view). Left port is positive terminal, right is negative (GND).
2. JTAG header The pin assignment of the JTAG header matches the 14 pin pos. connectors of common programming cables. Some examples have been shown in section 2.1. Programming the board. Fig. 9: Standard Xilinx JTAG Header, dual row with 14 pins (2.00 mm pitch).
3. User LEDs (blue) Below the JTAG connector there are three blue LEDs. They are marked with designators LD0, LD1, and LD2. LD0 indicates completion of the configuration sequence. After programming has finished, the LED will be on (until the FPGA is configured, the LED will be off). In normal operation the LED LD0 is permanently switch on. The other two LEDs can be switched with output pins of the FPGA. The output drivers of the FPGA pins are used to power the LEDs directly. Tab. 3 shows the output pins from the FPGA connected to the LEDs.
4. User LEDs (green and red) In addition to the blue LEDs there is a green LED (LD3) and a red LED (LD4) on the board. Both are next to each other in the upper left corner of the board. Just like LD1 and LD2, LD3 and LD4 are driven by the output pins of the FPGA through a series resistor. The pin assignment of the green and the red LED is shown in Tab. 4.
5. Reset button The button SW1 on top right corner of the board triggers a manual reset of the FPGA. Fig. 10: Reset button SW1. In the unpressed state the PROGRAM_B pin of the FPGA is pulled high, and while pushing the button this pin is tied to GND. On falling edge, the FPGA configuration is cleared and configuration sequence is initiated upon the following rising edge. Because the FPGA is permanently configured to Master SPI mode, a new sequence will load configuration data from SPI flash.
6. Micro switches The four micro DIP switches SW2 can be used for user inputs. Fig. 11: Micro DIP switches SW2. Due to the small dimensions of the switches, these can probably be used for coding fixed values or states rather than for user inputs. During OFF-state of the switches, the associated pins of the FPGA are pulled high. In ON-state, they are tied to GND. The ON position of the switches is marked on the case, and the assigned pins are shown in Tab. 6.
7. Configuration memory (SPI flash) The non-volatile configuration for the FPGA can only be loaded in Master SPI mode (FPGA pins M[2:0]=001) from the attached memory device U2 (SPI flash). Fig. 12: 64 Mbit SPI configuration flash. During configuration, internal pull-up resistors are disabled on each SelectIO pin, because pin L15 PUDC_B is permanently pulled high. The flash is from S25FL064L series from Cypress Semiconductor. Since Xilinx Vivado version 2017.3 these series is supported (see Xilinx UG908, Table C-1: Supported Flash Memory Devices for Artix-7 Device Configuration). The flash memory has a density of 64 Mbit. The entire configuration bitstream length for the Xilinx XC7A35T is 17,536,096 bit (see Xilinx UG470, Table 1-1: Bitstream Length). In Xilinx Vivado, you have to choose s25fl064l-spi-x1_x2_x4 device for configuration memory (see section 2.1. Programming the board for details). The FPGA pins used to control the SPI flash are listed in Tab. 7
8. Clock source 100 MHz A Low-Jitter precision oscillator generates a stable system clock for the FPGA. The board has a DSC1123CI5-100.000 MEMS oscillator (U3) with 100 MHz output clock frequency. Fig. 13: 100 MHz clock source. The operating temperature is from -40° to 80° with a frequency stability of ±10 ppm. The clock soure has a LVDS output with ΔVpp of 350 mV. The output is terminated with a 100 Ω resistor (R14) on the FPGA board. The differential clock signal is routed to a Multi-region Clock Capable (MRCC) clock input on bank 14 (see Tab. 8).
9. PT header (26 pos.) The header on top of the board (PT) is a shrouded dual row 26 pin header with 2.54 mm pitch. Fig. 14: PT header with 26 positions. There are 22 general purpose input/outputs (GPIOs) and two separate power pins with corresponding GND pins. The voltage of the power pins can be hardware-selected with the resistor jumpers (0 Ω) RS and RS1 (see Tab. 1). FPGA pins with an *AD* in the designator can be used as analog inputs. For more information see Xilinx XADC documentation (Xilinx UG480).
A. PR header (16 pos.) The header on the right of the board (PR) is a shrouded dual row 16 pin header with 2.54 mm pitch. Fig. 16: PR header with 16 positions. There are 14 general purpose input/outputs (GPIOs) and a separate power pin with corresponding GND pin. The voltage of the power pin can be hardware-selected with the resistor jumpers (0 Ω) RS2 and RS3 (see Tab. 1). FPGA pins with an *AD* in the designator can be used as analog inputs. For more information see Xilinx XADC documentation (Xilinx UG480).
B. External clock IO (optional MMCX jacks) The optional MMCX jacks can be used for clock input or output signals, or even as general purpose I/Os. Fig. 17. Optional MMCX jacks for clock input and output signals (left picture). With an appropriate adapter, the connectors are also suitable for SMA cables (right picture).
C. DC/DC converter for I/O voltage All I/O banks (bank 0, 14, 15, 34, and 35) of the FPGA are powered by 3.3 V. The voltage is provided by an onboard DC/DC converter which is capable of driving an output current of 2 A. All current sinks connected to the board and the FPGA itself must be considered to not exceed the current limit of 2 A! Further, we recommend the following constraints regarding the configuration of the FPGA: set_property CFGBVS VCCO [current_design]; set_property CONFIG_VOLTAGE 3.3 [current_design]; For single ended IO we recommend following constraint template for IOSTANDARD of a pin: set_property IOSTANDARD LVCMOS33 [get_ports *]; and for differential IO use Transition Minimized Differential Signaling (TMDS) standard: set_property IOSTANDARD TMDS_33 [get_ports *];
|4. Typical characteristics
to be done after first mass production run!
|5. Mechanical data
Following drawings show relevant mechanical dimensions of the board. All dimensions are in millimeters (mm). Fig. 18: Mechanical dimension of the FPGA module (board outline and mounting holes). Fig. 19: Mechanical dimension of the FPGA module (connectors and pin positions).
|6. Ordering information
The T0005 Artix-7 FPGA Module can be ordered at various online market places, or you can request a quotation by sending an e-mail to email@example.com.
Tab. 12: Assembly variants of Artix-7 FPGA Module with product numbers and market places.
|7. Document history Document number: DS#T0005 Version history: 2018/04/17: Initial release|
|8. Imprint Name and registered office of the company: IAM Electronic GmbH Bucksdorffstr. 43 04159 Leipzig Germany Contact: Phone: +49 341 26496031 E-Mail: firstname.lastname@example.org Chief Executive Officer: Dr. Philipp Födisch Commercial register: Register court: Amtsgericht Leipzig Register number: HRB 34071 Value Added Tax Identification Number: DE313797981|